Name
Abstract | ||
|---|---|---|
Analog layout automation is a popular research direction in recent years to raise the design productivity. However, the research on this topic is still not well accepted by analog designers because notable performance loss often exists in tool-generated layout. Most previous works focus on layout placement problem and route the nets implicitly by typical digital routing methodology. This routing approach can solve the net crossing issue easily, but requires a lot of extra vias to connect the horizontal and vertical lines, which significantly increases the wire loads and reduces the circuit performance. In the proposed analog routing flow, we try to route each net with minimum layer changing and consider the wire length simultaneously. In other words, wire load is used as the optimization goal instead of using wire length only to keep the circuit performance after laying out the design. As demonstrated on several cases, this approach significantly reduces the wire load and keeps the similar circuit performance as in manual works.
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Year | Venue | Field |
|---|---|---|
2018 | ASP-DAC | Parallel simulation,Analogue electronics,Computer science,Steiner tree problem,Layout automation,Flow (psychology),Electronic engineering,Automation,Circuit performance,The Internet |
DocType | ISSN | ISBN |
Conference | 2153-6961 | 978-1-4503-6007-4 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao-Yu Chi | 1 | 0 | 0.34 |
| Hwa-Yi Tseng | 2 | 0 | 0.34 |
| Chien-Nan Jimmy Liu | 3 | 97 | 27.07 |
| Hung-Ming Chen | 4 | 493 | 59.19 |