Paper Info
Title
An FPGA-based processor for training convolutional neural networks
Abstract
Convolutional neural networks (CNNs) have gained great success in various computer vision applications. However, training a CNN model is computation-intensive and time-consuming. Hence training is mainly processed on large clusters of high-performance processors like server CPUs and GPUs. In this paper, we propose an FPGA-based processor design to accelerate the training process of CNNs. We first analyze the operations in all types of CNN layers in the training process. A uniform computation engine design is proposed to efficiently carry out all kinds of operations based on the analysis. Then a scalable accelerator framework is presented that exploits the parallelism further by unrolling the loops in two levels. The proposed accelerator design is demonstrated by implementing a processor on the Xilinx ZU19EG FPGA working at 200 MHz. The evaluation results on a group of CNN models show that our processor is 5.7 to 10.7-fold faster than the software implementations on the Intel Core i5-4440 CPU(@3.10GHz).
Year
DOI
Venue
2017
10.1109/FPT.2017.8280142
2017 International Conference on Field Programmable Technology (ICFPT)
Keywords
Field
DocType
computer vision applications,CNN model,high-performance processors,processor design,training process,CNN layers,uniform computation engine design,scalable accelerator framework,accelerator design,FPGA-based processor,convolutional neural network training,Xilinx ZU19EG FPGA,frequency 200.0 MHz,frequency 3.1 GHz
Convolutional code,Convolutional neural network,Computer science,Parallel computing,Field-programmable gate array,Exploit,Processor design,Software implementation,Scalability,Computation
Conference
ISBN
Citations 
PageRank 
978-1-5386-2657-3
1
0.36
References 
Authors
6
5
Name
Order
Citations
PageRank
Zhiqiang Liu111624.93
Yong Dou263289.67
Jingfei Jiang3395.66
Qiang Wang463.54
Paul Chow5868119.97