Title
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.
Abstract
A frame object detection problem consists of two problems: one is a regression problem to spatially separated bounding boxes, the second is the associated classification of the objects within realtime frame rate. It is widely used in the embedded systems, such as robotics, autonomous driving, security, and drones - all of which require high-performance and low-power consumption. This paper implements the YOLO (You only look once) object detector on an FPGA, which is faster and has a higher accuracy. It is based on the convolutional deep neural network (CNN), and it is a dominant part both the performance and the area. However, the object detector based on the CNN consists of a bounding box prediction (regression) and a class estimation (classification). Thus, the conventional all binarized CNN fails to recognize in most cases. In the paper, we propose a lightweight YOLOv2, which consists of the binarized CNN for a feature extraction and the parallel support vector regression (SVR) for both a classification and a localization. To our knowledge, this is the first time binarized CNN»s have been successfully used in object detection. We implement a pipelined based architecture for the lightweight YOLOv2 on the Xilinx Inc. zcu102 board, which has the Xilinx Inc. Zynq Ultrascale+ MPSoC. The implemented object detector archived 40.81 frames per second (FPS). Compared with the ARM Cortex-A57, it was 177.4 times faster, it dissipated 1.1 times more power, and its performance per power efficiency was 158.9 times better. Also, compared with the nVidia Pascall embedded GPU, it was 27.5 times faster, it dissipated 1.5 times lower power, and its performance per power efficiency was 42.9 times better. Thus, our method is suitable for the frame object detector for an embedded vision system.
Year
Venue
Field
2018
FPGA
Computer vision,Object detection,Machine vision,Computer science,Support vector machine,Field-programmable gate array,Feature extraction,Real-time computing,Frame rate,Artificial intelligence,MPSoC,Minimum bounding box
DocType
ISBN
Citations 
Conference
978-1-4503-5614-5
2
PageRank 
References 
Authors
0.49
17
4
Name
Order
Citations
PageRank
Hiroki Nakahara115537.34
Haruyoshi Yonekawa2344.37
Tomoya Fujii351.90
Shimpei Sato44313.03