Title
Design and theoretical comparison of input ESD devices in 180 nm CMOS with focus on low capacitance.
Abstract
With the last decade’s advances in sensor technologies and packaging techniques, there are several applications where the input capacitance and the leakage current of the integrated circuit (IC) front-end limit the readout accuracy of sensor systems. In particular, optimization of the electrostatic discharge (ESD) protection devices at the IC input could improve performance. Specifically, such optimization should involve reduction of parasitic capacitance and leakage current while maintaining the ESD robustness. Several ESD devices have been analyzed against input capacitance, leakage current and robust ESD performance. The first device of interest is a diode, as the simplest solution and then there are three MOS transistor based devices, gate-grounded NMOS (GGNMOS), gate-coupled NMOS (GCNMOS), and substrate pump NMOS (SPNMOS). The target fabrication process is 180 nm CMOS. Theoretical analysis of capacitance simulated with Cadence® in 180 nm CMOS design kit including layout extracted parasitics in combination with TCAD Sentaurus® simulations of current density and temperature is presented for selected ESD devices.
Year
DOI
Venue
2018
10.1007/s00502-017-0569-0
Elektrotechnik und Informationstechnik
Keywords
Field
DocType
electrostatic discharge, integrated circuit, robust, ESD diode, GGNMOS, elektrostatische Entladung, Integrierte Schaltung, Robustheit, ESD-Schutz, GGNMOS
Parasitic capacitance,Capacitance,Leakage (electronics),NMOS logic,Electrostatic discharge,CMOS,Electronic engineering,Engineering,Parasitic extraction,ggNMOS
Journal
Volume
Issue
ISSN
135
1
0932-383X
Citations 
PageRank 
References 
0
0.34
1
Authors
3