Abstract | ||
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Design of Turbo-Code decoders for the 3GPP LTE/LTE-A standard focuses on achieving a high-throughput of up to 1 Gbps with low decoding latencies at very high code rates. At code rates close to one, as specified in LTE/LTE-A, the decoding process can oscillate. Although the decoder converges to a valid code word after half-iteration i, after half-iteration \(i+1\) the decoded code word is invalid again. To circumvent this, the CRC that is attached to each code word must be evaluated after each half-iteration. We present a generalized architecture for calculating the CRC On-the-fly during both non-interleaved and interleaved half-iterations and thus explicitly taking into account the requirements for low-latency Turbo-Code decoding. Further, we investigate the latency-, and energy savings provided by employing this calculation scheme. Lastly, we give post layout synthesis results for a case study implementation in state-of-the-art 28 nm FDSOI technology. |
Year | DOI | Venue |
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2018 | 10.1007/s10776-017-0374-z | IJWIN |
Keywords | Field | DocType |
LTE-A Turbo-Code decoder,Low latency,On-the-fly CRC | Computer science,Latency (engineering),Parallel computing,Turbo code,Real-time computing,Code word,Soft-decision decoder,Decoding methods,Latency (engineering) | Journal |
Volume | Issue | ISSN |
25 | 1 | 1068-9605 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
2 |
Name | Order | Citations | PageRank |
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Stefan Weithoffer | 1 | 4 | 2.15 |
Norbert Wehn | 2 | 1165 | 137.17 |