Name
Abstract | ||
|---|---|---|
This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. |
Year | DOI | Venue |
|---|---|---|
2018 | https://doi.org/10.1007/s11265-017-1282-2 | Signal Processing Systems |
Keywords | Field | DocType |
Iris localization,Iris segmentation,Hardware accelerators,Edge-map generation hardware,Circular Hough transform hardware,FPGA implementation | Computer vision,Iris recognition,Median filter,Hardware implementations,Computer science,Iris localization,Field-programmable gate array,Hough transform,Boundary detection,Artificial intelligence,Pixel,Computer hardware | Journal |
Volume | Issue | ISSN |
90 | 4 | 1939-8018 |
Citations | PageRank | References |
2 | 0.36 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vineet Kumar | 1 | 196 | 26.07 |
| Abhijit R. Asati | 2 | 13 | 5.70 |
| Anu Gupta | 3 | 6 | 1.78 |