Name
Playground
About
FAQ
GitHub
Playground
Shortest Path Finder
Community Detector
Connected Papers
Author Trending
Claudimar Pereira da Veiga
Samir Gourdache
Claudia Calabrese
kaoru fujiie
Maria Concetta Palumbo
Jhonathan Pinzon
Giovanni Venturelli
Chen Ma
Radu Timofte
Kuanrui Yin
Home
/
Author
/
ABHIJIT R. ASATI
Author Info
Open Visualization
Name
Affiliation
Papers
ABHIJIT R. ASATI
Department of Electrical and Electronics Engineering, Birla Institute Of Technology And Science, Pilani, India
16
Collaborators
Citations
PageRank
14
13
5.70
Referers
Referees
References
34
229
86
Search Limit
100
229
Publications (16 rows)
Collaborators (14 rows)
Referers (34 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm
0
0.34
2021
High-Speed And Area-Efficient Sobel Edge Detector On Field-Programmable Gate Array For Artificial Intelligence And Machine Learning Applications
1
0.35
2021
High-Throughput Field-Programable Gate Array Implementation Of The Advanced Encryption Standard Algorithm For Automotive Security Applications
1
0.36
2021
High-Level synthesis assisted design and verification framework for automotive radar processors
0
0.34
2020
Speed optimal FPGA implementation of the encryption algorithms for telecom applications
1
0.37
2020
Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation.
3
0.39
2018
Hardware Accelerators for Iris Localization.
2
0.36
2018
Low-latency median filter core for hardware implementation of 5 × 5 median filtering.
1
0.35
2017
Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems.
0
0.34
2017
A Novel Edge-Map Creation Approach for Highly Accurate Pupil Localization in Unconstrained Infrared Iris Images
1
0.37
2016
Leakage immune modified pass transistor based 8t SRAM cell in subthreshold region
0
0.34
2015
An Iris localization method for noisy infrared iris images
0
0.34
2015
Design of a Static Current Simulator Using Device Matrix Approach
0
0.34
2012
A Novel Redundant Binary Number to Natural Binary Number Converter
3
0.45
2010
Dual channel addition based FFT processor architecture for signal and image processing
0
0.34
2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load
0
0.34
2009
1