Name
Abstract | ||
|---|---|---|
The cost of Burn-In is a major concern for the testing of Automotive Systems-on-Chip (SoC). This paper highlights problematic aspects of a Burn-In flow and describes a two-layered adaptive technique that permits to optimize the stress application and strongly reduce BI test time. At the SoC level, the described methodology adaptively copes with FLASH erase time uncertainties; at the Automatic Test Equipment (ATE) level, the strategy relies on power monitors and tester intelligence. The paper reports experimental results on a SoC manufactured by STMicroelectronics; figures show an optimized usage of stress resources and demonstrates a reduction of 25% in the BI test time when using the proposed adaptive techniques. |
Year | DOI | Venue |
|---|---|---|
2018 | https://doi.org/10.1007/s10836-018-5705-1 | J. Electronic Testing |
Keywords | Field | DocType |
SoC,Safety critical environment,Burn-in,Adaptive techniques | Automatic test equipment,Computer science,Burn-in,Electronic engineering,Adaptive management,Reliability engineering,Automotive industry | Journal |
Volume | Issue | ISSN |
34 | 1 | 0923-8174 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Davide Appello | 1 | 37 | 8.48 |
| Paolo Bernardi | 2 | 48 | 8.89 |
| Conrad Bugeja | 3 | 1 | 1.06 |
| Riccardo Cantoro | 4 | 99 | 18.20 |
| Giorgio Pollaccia | 5 | 1 | 1.06 |
| Marco Restifo | 6 | 6 | 3.31 |
| Federico Venini | 7 | 1 | 1.06 |