Name
Title | ||
|---|---|---|
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization |
Abstract | ||
|---|---|---|
Canonic signed digit (CSD) representation involves very few non-zero bits, making it an ideal candidate for aiding speed and area optimization in VLSI based DSP architectures. In this paper, we present high speed, FPGA fabric aware pipelined architectures for CSD recoding circuits starting from a two's complement number or a redundant signed digit input. Using the configured, yet under-utilized logic elements of the FPGA that realized the CSD recoding circuit, we additionally introduce fault localization circuitry to trace the source of any hard or soft errors that often creep in owing to various reliability hazards. The entire exercise has been carried out through target FPGA specific primitive instantiation coupled with placement constraints that guarantees high speed design, as well as eases the exercise to locate faulty FPGA slice coordinates, if any. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSID.2018.60 | 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
Canonic signed digit,redundant signed digit,carry look-ahead,FPGA,carry chain,primitive instantiation,C-testability,self dual,scan chain | Digital signal processing,Computer science,Field-programmable gate array,Electronic engineering,Computer hardware,Electronic circuit,Multiplexing,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-5386-3693-0 | 1 |
PageRank | References | Authors |
0.41 | 6 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayan Palchaudhuri | 1 | 11 | 7.67 |
| Anindya Sundar Dhar | 2 | 97 | 26.09 |