Paper Info
Title
GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime
Abstract
Multi-core memory systems commonly share resources between processors. Resource sharing improves utilization at the cost of increased inter-application interference which may lead to priority inversion, missed deadlines and unpredictable interactive performance. A key component to effectively manage multi-core resources is performance accounting which aims to accurately estimate interference-free application performance. Previously proposed accounting systems are either invasive or transparent. Invasive accounting systems can be accurate, but slow down latency-sensitive processes. Transparent accounting systems do not affect performance, but tend to provide less accurate performance estimates. We propose a novel class of performance accounting systems that achieve both performance-transparency and superior accuracy. We call the approach dataflow accounting, and the key idea is to track dynamic dataflow properties and use these to estimate interference-free performance. Our main contribution is Graph-based Dynamic Performance (GDP) accounting. GDP dynamically builds a dataflow graph of load requests and periods where the processor commits instructions. This graph concisely represents the relationship between memory loads and forward progress in program execution. More specifically, GDP estimates interference-free stall cycles by multiplying the critical path length of the dataflow graph with the estimated interference-free memory latency. GDP is very accurate with mean IPC estimation errors of 3.4% and 9.8% for our 4- and 8-core processors, respectively. When GDP is used in a cache partitioning policy, we observe average system throughput improvements of 11.9% and 20.8% compared to partitioning using the state-of-the-art Application Slowdown Model.
Year
DOI
Venue
2018
10.1109/HPCA.2018.00034
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)
Keywords
Field
DocType
Multi-core memory systems,Accounting
Accounting information system,Cache,Computer science,Parallel computing,Dataflow,Priority inversion,Throughput,Critical path method,Shared resource,Computer engineering,CAS latency
Conference
ISSN
ISBN
Citations 
1530-0897
978-1-5386-3660-2
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Magnus Jahre122620.50
Lieven Eeckhout22863195.11