Name
Title | ||
|---|---|---|
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices |
Abstract | ||
|---|---|---|
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have numerous advantages over PUF designs that exploit alternative substrates: DRAM is a major component of many modern systems, and a DRAM-based PUF can generate many unique identiers. However, none of the prior DRAM PUF proposals provide implementations suitable for runtime-accessible PUF evaluation on commodity DRAM devices. Prior DRAM PUFs exhibit unacceptably high latencies, especially at low temperatures (e.g., >125.8s on average for a 64KiB memory segment below 55C), and they cause high system interference by keeping part of DRAM unavailable during PUF evaluation. In this paper, we introduce the DRAM latency PUF, a new class of fast, reliable DRAM PUFs. The key idea is to reduce DRAM read access latency below the reliable datasheet specications using software-only system calls. Doing so results in error patterns that reect the compound eects of manufacturing variations in various DRAM structures (e.g., capacitors, wires, sense ampli- ers). Based on a rigorous experimental characterization of 223 modern LPDDR4 DRAM chips, we demonstrate that these error patterns 1) satisfy runtime-accessible PUF requirements, and 2) are quickly generated (i.e., at 88.2ms) irrespective of operating temperature using a real system with no additional hardware modications. We show that, for a constant DRAM capacity overhead of 64KiB, our implementation of the DRAM latency PUF enables an average (minimum, maximum) PUF evaluation time speedup of 152x (109x, 181x) at 70C and 1426x (868x, 1783x) at 55C when compared to a DRAM retention PUF and achieves greater speedups at even lower temperatures. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/HPCA.2018.00026 | 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA) |
Keywords | Field | DocType |
DRAM latency PUF,latency-reliability tradeoff,modern commodity DRAM devices,PUF designs,prior DRAM PUF proposals,runtime-accessible PUF evaluation,DRAM structures,runtime-accessible PUF requirements,constant DRAM capacity,DRAM retention PUF,physically unclonable functions,reliable DRAM PUF,modern LPDDR4 DRAM chips,software-only system,constant DRAM capacity overhead,time 125.8 s,time 88.2 ms | Dram,Capacitor,Authentication,Cryptography,Latency (engineering),Computer science,Server,Parallel computing,Datasheet,Speedup,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-5386-3660-2 | 17 |
PageRank | References | Authors |
0.45 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jeremie Kim | 1 | 263 | 13.68 |
| Minesh Patel | 2 | 204 | 9.82 |
| Hasan Hassan | 3 | 352 | 17.76 |
| Onur Mutlu | 4 | 9446 | 357.40 |