Minesh Patel - Citegraph

Author Info

Name	Affiliation	Papers
MINESH PATEL	Carnegie Mellon University, Pittsburgh, PA	24
Collaborators	Citations	PageRank
67	204	9.82
Referers	Referees	References
350	1311	808

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Publications (24 rows)

Collaborators (67 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting Codes	0	0.34	2021
A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses	3	0.37	2021
SIMDRAM: a framework for bit-serial SIMD processing using DRAM	16	0.51	2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations	2	0.35	2021
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows	1	0.34	2021
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips	7	0.37	2021
CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off	9	0.39	2020
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching	2	0.35	2020
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques	13	0.50	2020
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework	2	0.35	2020
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics	4	0.37	2020
Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers	10	0.45	2020
Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices	7	0.41	2019
CoNDA: efficient cache coherence support for near-data accelerators	12	0.43	2019
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices.	0	0.34	2019
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput	18	0.43	2019
CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability	12	0.42	2019
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines	6	0.36	2018
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices	17	0.45	2018
D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices.	0	0.34	2018
Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration.	9	0.39	2018
LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures.	0	0.34	2017
The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions.	21	0.51	2017
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory.	33	0.71	2017