Paper Info
Title
A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs.
Abstract
Many modern FPGA-based soft-processor designs must include dedicated hardware modules to satisfy the requirements of a wide range of applications. Not seldom they all do not fit in the FPGA target, so their functionalities must be mapped into the much slower software domain. However, many complex soft-core processors usually underuse the available Block RAMs (BRAMs) when comparing to LUTs and registers. By taking advantage of this fact, we propose a generic low-cost BRAM-based function reuse mechanism (the BRAM-FR) that can be easily configured for precise or approximate modes to accelerate execution. The BRAM-FR was implemented in HDL and coupled to a configurable 4-issue VLIW processor. It was used to optimize different applications that use a soft-float library to emulate a Floating-Point Unit (FPU), and an image processing filter that tolerates a certain level of error. We show that our technique can accelerate the former by 1.23x and the latter by 1.52x, with a Reuse Table that fits in the BRAMs (that would otherwise be idle) of five tested FPGA targets with a marginal increase in the number of slice registers and LUTs.
Year
Venue
Field
2018
ARC
Reuse,Computer science,Idle,Very long instruction word,Parallel computing,Field-programmable gate array,Image processing,Software,Soft core,Hardware modules,Embedded system
DocType
Citations 
PageRank 
Conference
1
0.36
References 
Authors
9
7
Name
Order
Citations
PageRank
Pedro Henrique Exenberger Becker122.07
Anderson Luiz Sartor2317.67
Marcelo Brandalero3710.66
Tiago Trevisan Jost410.36
Stephan Wong58912.74
Luigi Carro61393166.42
Antonio C. S. Beck7155.10