Name
Abstract | ||
|---|---|---|
Boolean Relation (BR) is a many-to-many mapping between two domains. Logic optimization considering BR can exploit the potential flexibility existed in logic networks to minimize the circuits. In this paper, we present a logic optimization approach considering BR. The approach identifies a proper sub-circuit and locally changes its functionality by solving the corresponding BR in the sub-circuit without altering the overall functionality of the circuit. We conducted experiments on a set of MCNC benchmarks that cannot be further optimized by resyn2 script in ABC. The experimental results show that the node counts of these benchmarks can be further reduced. Additionally, when we apply our approach followed by the resvn2 script repeatedly, we can obtain 6.11% improvements in average. |
Year | Venue | Field |
|---|---|---|
2018 | PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | Boolean function,Observability,Logic gate,Computer science,Logic optimization,Parallel computing,Exploit,Electronic circuit,Benchmark (computing) |
DocType | ISSN | Citations |
Conference | 1530-1591 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tung-Yuan Lee | 1 | 0 | 0.34 |
| Chia-Cheng Wu | 2 | 3 | 3.16 |
| Chia-Chun Lin | 3 | 128 | 15.00 |
| Yung-Chih Chen | 4 | 413 | 39.89 |
| Wang Chun-Yao | 5 | 251 | 36.08 |