Name
Abstract | ||
|---|---|---|
One of the major challenges in device down-scaling is the increase in the leakage power, which becomes a major component in the overall system power consumption. One way to deal with this problem is to introduce the concept of normally-off instant-on computing architectures, in which the system components are powered off when they are not active. An associated challenge is the back-up and restoration of system states, which in turn can introduce additional costs that erode some of the gains. A promising alternative is the use of non-volatile storage elements in the System-on-Chip (SoC) design which can instantly power-down and retain their values. In this work, we show how we can design a normally-off SoC by exploiting non-volatile latches, flip-flops and registers. The idea is to design a hybrid architecture containing conventional CMOS bistables as well as different flavors of spintronic-based non-volatile storage elements, to balance performance, area, and energy efficiency. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.23919/DATE.2018.8341989 | 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Keywords | Field | DocType |
device down-scaling,leakage power,system power consumption,system states,nonvolatile latches,hybrid architecture,spintronic-based nonvolatile storage elements,spintronic normally-off heterogeneous system-on-chip design,normally-off instant-on computing architectures,nonvolatile storage elements,normally-off SoC,flip-flops,registers,CMOS bistables | Architecture,Computer science,Efficient energy use,Spintronics,CMOS,Balance performance,Real-time computing,Non-volatile memory,System on chip design,Embedded system,Power consumption | Conference |
ISSN | Citations | PageRank |
1530-1591 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anteneh Gebregiorgis | 1 | 22 | 4.91 |
| Rajendra Bishnoi | 2 | 132 | 19.64 |
| Mehdi B. Tahoori | 3 | 1537 | 163.44 |