Name
Abstract | ||
|---|---|---|
We describe the first hardware implementation of a quantum-secure encryption scheme along with its low-cost power side-channel countermeasures. The encryption uses an implementation-friendly Binary-Ring-Learning-with-Errors (B-RLWE) problem with binary errors that can be efficiently generated in hardware. We demonstrate that a direct implementation of B-RLWE exhibits vulnerability to power side-channel attacks, even to Simple Power Analysis, due to the nature of binary coefficients. We mitigate this vulnerability with a redundant addition and memory update. To further protect against Differential Power Analysis (DPA), we use a B-RLWE specific opportunity to construct a lightweight yet effective countermeasure based on randomization of intermediate states and masked threshold decoding. On a SAKURA-G FPGA board, we show that our method increases the required number of measurements for DPA attacks by 40 χ compared to unprotected design. Our results also quantify the trade-off between side-channel security and hardware area-cost of B-RLWE. |
Year | Venue | Field |
|---|---|---|
2018 | DATE | Power analysis,Adder,Computer science,Field-programmable gate array,Encryption,Side channel attack,Decoding methods,Computer hardware,Public-key cryptography,Binary number |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
13 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Aydin Aysu | 1 | 124 | 15.59 |
| Michael Orshansky | 2 | 1299 | 110.06 |
| Mohit Tiwari | 3 | 445 | 23.94 |