Name
Title | ||
|---|---|---|
Efficient Synthesis Of Approximate Threshold Logic Circuits With An Error Rate Guarantee |
Abstract | ||
|---|---|---|
Recently, Threshold logic attracts a lot of attention due to the advances of its physical implementation and the strong binding to neural networks. Approximate computing is a new design paradigm that focuses on error-tolerant applications, e.g., machine learning or pattern recognition. In this paper, we integrate threshold logic with approximate computing and propose a synthesis algorithm to obtain cost-efficient approximate threshold logic circuits with an error rate guarantee. We conduct experiments on IWLS 2005 benchmarks. The experimental results show that the proposed algorithm can efficiently explore the approximability of each benchmark. For a 5% error rate constraint, the circuit cost can be reduced by up to 65%, and 22.8% on average. Compared with a naive method, our approach has a speedup of 2.42 under a 5% error rate constraint. |
Year | Venue | Field |
|---|---|---|
2018 | PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) | Approximation algorithm,Logic gate,Design paradigm,Computer science,Parallel computing,Word error rate,Algorithm,Artificial neural network,Speedup,Approximate computing |
DocType | ISSN | Citations |
Conference | 1530-1591 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yung-An Lai | 1 | 0 | 0.68 |
| Chia-Chun Lin | 2 | 128 | 15.00 |
| Chia-Cheng Wu | 3 | 3 | 3.16 |
| Yung-Chih Chen | 4 | 413 | 39.89 |
| Wang Chun-Yao | 5 | 251 | 36.08 |