Title
A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture.
Abstract
This paper presents a 4.1 megapixel, 280 frames/s, back-illuminated, stacked, global shutter (GS) CMOS image sensor with array-parallel analog-to-digital converter (ADC) architecture for region-control applications. The sensor solves an image distortion problem caused by rolling shutter in a pixel sub-array by utilizing a floating diffusion (FD) memory to implement GS operation. A newly developed ...
Year
DOI
Venue
2018
10.1109/JSSC.2017.2784759
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Transistors,Sensor arrays,Distortion,Image sensors,Logic gates
Correlated double sampling,Rolling shutter,Logic gate,Image sensor,Intelligent sensor,Computer science,Shutter,Electronic engineering,Pixel,Amplifier
Journal
Volume
Issue
ISSN
53
4
0018-9200
Citations 
PageRank 
References 
1
0.35
0
Authors
15