| A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture. | 1 | 0.35 | 2018 |
| Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs. | 0 | 0.34 | 2018 |
| High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor | 32 | 9.25 | 2006 |
| A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change | 5 | 0.95 | 2006 |
