Name
Title | ||
|---|---|---|
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. |
Abstract | ||
|---|---|---|
This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/JSSC.2017.2778286 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Delays,Decision feedback equalizers,Integrated circuit modeling,Analytical models,Transfer functions,Jitter | Computer science,CMOS,Full custom,Electronic engineering,Digital clock,Latency (engineering),Jitter,Vertical-cavity surface-emitting laser,Cutoff frequency,Electronic circuit | Journal |
Volume | Issue | ISSN |
53 | 4 | 0018-9200 |
Citations | PageRank | References |
1 | 0.41 | 0 |
Authors | ||
17 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ilter Özkaya | 1 | 16 | 5.72 |
| Alessandro Cevrero | 2 | 107 | 16.21 |
| Pier Andrea Francese | 3 | 138 | 25.33 |
| Christian Menolfi | 4 | 245 | 41.54 |
| Thomas Morf | 5 | 244 | 42.54 |
| Matthias Braendli | 6 | 158 | 24.28 |
| Daniel M. Kuchta | 7 | 36 | 7.79 |
| Lukas Kull | 8 | 141 | 18.63 |
| Christian W. Baks | 9 | 28 | 8.52 |
| Jonathan Proesel | 10 | 49 | 10.68 |
| Marcel A. Kossel | 11 | 179 | 33.86 |
| Danny Luu | 12 | 16 | 7.55 |
| Benjamin G. Lee | 13 | 153 | 17.04 |
| Fuad E. Doany | 14 | 23 | 6.68 |
| Mounir Meghelli | 15 | 78 | 14.76 |
| Yusuf Leblebici | 16 | 771 | 119.09 |
| Thomas Toifl | 17 | 275 | 48.02 |