Name
Abstract | ||
|---|---|---|
Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/CICC.2018.8357063 | 2018 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | Field | DocType |
accelerated circuit aging,circuit operation,aging effects,iterative simulations,elevated degradation rate,circuit topology,circuit simulation,benchmark circuits,reliability physics,silicon data,size 65.0 nm,size 28.0 nm,size 14.0 nm,size 16 nm,Si | Modeling and simulation,Computer science,Electronic engineering,Accelerated aging,Electronic circuit,Computation,Topology (electrical circuits),Scalability | Conference |
ISBN | Citations | PageRank |
978-1-5386-2484-5 | 0 | 0.34 |
References | Authors | |
1 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Devyani Patra | 1 | 0 | 1.01 |
| Jiayang Zhang | 2 | 0 | 0.34 |
| Runsheng Wang | 3 | 169 | 21.11 |
| Mehdi Katoozi | 4 | 0 | 1.01 |
| Ethan H. Cannon | 5 | 13 | 3.27 |
| Ru Huang | 6 | 188 | 48.74 |
| Yu Cao | 7 | 329 | 29.78 |