Name
Abstract | ||
|---|---|---|
Time speculation has been widely used to achieve high performance in modern design as it exploits average-case timing optimization instead of worst-case timing optimization focusing on reducing longest path delay which rarely happens. Variable-latency design (VLD) style is one research category of time speculation. Since process and environmental variations are hard to predict, traditional variabl... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCAD.2017.2748028 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Delays,Logic gates,Clocks,Monitoring,Detectors | Speculation,Logic gate,Software deployment,Computer science,Real-time computing,Exploit,Detector,Longest path problem,Performance improvement | Journal |
Volume | Issue | ISSN |
37 | 6 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chung-Han Chou | 1 | 39 | 3.73 |
| Tsui-Yun Chang | 2 | 0 | 0.34 |
| Kai-Chiang Wu | 3 | 113 | 13.98 |
| Shih-Chieh Chang | 4 | 641 | 52.31 |