Title
Design of Low-Power WiNoC with Congestion-Aware Wireless Node.
Abstract
As the key component of wireless network-on-chip (WiNoC), wireless router is required to handle a large number of data packets which could cause network congestion. The congestion not only reduces the network performance, but also results in additional power consumption. In this paper, a low-power WiNoC with congestion-aware wireless node is proposed. Firstly, flit counter unit and address resolution unit are added in wireless interface (WI), which can sense the congestion information and destination address information of each wireless node dynamically. Secondly, through the proposed congestion judgment algorithm, the congestion judgment unit in global network can judge the priority of each wireless node pair and set the highest-priority wireless node pair to use the channel resources preferentially. The mechanism can effectively alleviate the congestion of wireless nodes and ensure the stability of system performance. In addition, a sleep mechanism is utilized to switch off WI which fails in the wireless channel competition. Experimental results show that the proposed scheme can effectively improve the performance in terms of packets' transmission latency and network throughput.
Year
DOI
Venue
2018
10.1142/S0218126618501487
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Keywords
Field
DocType
Wireless network-on-chip,wireless interface,congestion-aware,low-power
Wireless,Wireless network on chip,Computer science,Network packet,Wireless router,Computer network,Electronic engineering,Network congestion,Wireless network interface controller
Journal
Volume
Issue
ISSN
27
9
0218-1266
Citations 
PageRank 
References 
0
0.34
13
Authors
6
Name
Order
Citations
PageRank
Yiming Ouyang1187.51
Zhe Li23016.58
Kun Xing300.68
Zhengfeng Huang48430.14
Huaguo Liang521633.27
Jian-hua Li655898.16