| A reconfigurable PUF structure with dual working modes based on entropy separation model | 0 | 0.34 | 2022 |
| Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator | 0 | 0.34 | 2022 |
| A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design | 0 | 0.34 | 2022 |
| Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements | 0 | 0.34 | 2022 |
| A reconfigurable test method based on LFSR for 3D stacking integrated circuits | 0 | 0.34 | 2022 |
| High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure | 2 | 0.36 | 2021 |
| A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC | 1 | 0.36 | 2021 |
| Design of node separated triple-node-upset self-recoverable latch | 0 | 0.34 | 2021 |
| Architecting a priority-based dynamic media access control mechanism in Wireless Network-on-Chip | 0 | 0.34 | 2021 |
| LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS | 0 | 0.34 | 2021 |
| A high reliability physically unclonable function based on multiple tunable ring oscillator | 0 | 0.34 | 2021 |
| Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator | 1 | 0.36 | 2021 |
| Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System | 2 | 0.37 | 2021 |
| Design of MNU-Resilient latches based on input-split C-elements | 0 | 0.34 | 2021 |
| A high-speed and triple-node-upset recovery latch with heterogeneous interconnection | 0 | 0.34 | 2021 |
| Approximate multipliers based on a novel unbiased approximate 4-2 compressor | 0 | 0.34 | 2021 |
| Chip Test Pattern Reordering Method Using Adaptive Test To Reduce Cost For Testing Of Ics | 0 | 0.34 | 2021 |
| Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC | 4 | 0.40 | 2020 |
| Cm < Sup > 3 </Sup > Winocs: Congestion-Aware Millimeter-Wave Multichannel Wireless Networks-On-Chip | 0 | 0.34 | 2020 |
| LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults | 6 | 0.54 | 2020 |
| A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators | 0 | 0.34 | 2020 |
| Multi-task Scheduling for PIM-based Heterogeneous Computing System | 0 | 0.34 | 2020 |
| Architecture of Cobweb-Based Redundant TSV for Clustered Faults | 8 | 0.55 | 2020 |
| Design of a Wireless Router with Virtual Channel Fault Tolerant in WiNoC | 0 | 0.34 | 2020 |
| A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC. | 1 | 0.39 | 2020 |
| Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications | 0 | 0.34 | 2020 |
| Retraction: Reliability Assurance In Early-Life-Failure Test Through Improved Nearest Neighbor Regression (Retraction Of Vol 17, Pg 531, 2020) | 0 | 0.34 | 2020 |
| Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory | 0 | 0.34 | 2019 |
| A Pulse Shrinking-based Test Solution for Pre-bond Through Silicon Via in 3D ICs | 1 | 0.36 | 2019 |
| Design of Wireless Network on Chip with Priority-Based MAC | 0 | 0.34 | 2019 |
| A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells | 0 | 0.34 | 2019 |
| CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness | 0 | 0.34 | 2019 |
| DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip | 0 | 0.34 | 2019 |
| Temperature-Aware Floorplanning For Fixed-Outline 3d Ics | 0 | 0.34 | 2019 |
| A Hybrid DMR Latch to Tolerate MNU Using TDICE and WDICE | 0 | 0.34 | 2018 |
| An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs | 0 | 0.34 | 2018 |
| An improved communication scheme for non-HOL-blocking wireless NoC. | 0 | 0.34 | 2018 |
| MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System | 0 | 0.34 | 2018 |
| A High Reliability FPGA Chip Identification Generator Based on PDLs | 0 | 0.34 | 2018 |
| A Dictionary-Based Test Data Compression Method Using Tri-State Coding | 0 | 0.34 | 2018 |
| A Low-Cost High-Efficiency True Random Number Generator on FPGAs | 0 | 0.34 | 2018 |
| Design of Low-Power WiNoC with Congestion-Aware Wireless Node. | 0 | 0.34 | 2018 |
| Highly Robust Double Node Upset Resilient Hardened Latch Design | 0 | 0.34 | 2017 |
| Vernier Ring Based Pre-Bond Through Silicon Vias Test In 3d Ics | 0 | 0.34 | 2017 |
| A Single Event Transient Detector In Sram-Based Fpgas | 1 | 0.40 | 2017 |
| A TSV Fault-Tolerant Scheme Based on Failure Classification in 3D-NoC. | 2 | 0.39 | 2017 |
| A Transient Pulse Dually Filterable And Online Self-Recoverable Latch | 2 | 0.47 | 2017 |
| A Highly Reliable Butterfly Puf In Sram-Based Fpgas | 0 | 0.34 | 2017 |
| Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. | 6 | 0.48 | 2017 |
| A Region-Based Through-Silicon Via Repair Method For Clustered Faults | 0 | 0.34 | 2017 |
