Paper Info
Title
Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution.
Abstract
Many applications require both high performance and predictable timing. High-performance can be provided by COTS Multi-Core System on Chips (MPSoC), however, as cores in these systems share the memory bandwidth they are susceptible to interference from each other, which is a problem for timing predictability. We achieve predictability on multi-cores by employing the predictable execution model (PREM), which splits execution into a sequence of memory and compute phases, and schedules these such that only a single core is executing a memory phase at a time. We present a toolchain consisting of a compiler and an Integer Linear Programming scheduling model. Our compiler uses loop analysis and tiling to transform application code into PREM compliant binaries. Furthermore, we solve the problem of scheduling execution on multiple cores while preventing interference of memory phases. We evaluate our toolchain on Advanced-Driver-Assistance-Systems-like scenario containing matrix multiplications and FFT computations on NVIDIA TX1. The results show that our approach maintains similar average performance and improves variance of completion times by a factor of 9.
Year
DOI
Venue
2018
10.1145/3178442.3178444
PPoPP '18: 23nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming Vienna Austria February, 2018
Field
DocType
ISBN
Memory bandwidth,Scheduling (computing),Computer science,Parallel computing,Compiler,Schedule,Integer programming,Execution model,MPSoC,Toolchain
Conference
978-1-4503-5645-9
Citations 
PageRank 
References 
3
0.38
15
Authors
6
Name
Order
Citations
PageRank
Joel Matejka130.38
Björn Forsberg231.40
Michal Sojka394.13
Zdenk Hanzálek4576.67
Luca Benini5131161188.49
Andrea Marongiu633739.19