Name
Title | ||
|---|---|---|
Multi-Channel Multi-Gigabit Prbs Generator With A Built-In Clock In 0.18-Mu M Cmos Technology |
Abstract | ||
|---|---|---|
In this paper, a parallel pseudo-random bit sequence (PRBS) generator circuit with a built-in clock was designed in 0.18-mu m CMOS Technology. For high-speed operation, the current-mode logic (CML) was used in the circuit. In the PRBS generator, four-channel 2-Gb/s and two-channel 4-Gb/s PRBS signals can be generated. The power consumption of the chip is 554.3-mW at 1.8-V of power supply, and the chip area is 1.196x1.01-mm(2). The PRBS generator can be suitable in multi-level modulation and multi-channel transmission tests. |
Year | Venue | Keywords |
|---|---|---|
2017 | PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017) | pseudo-random bit sequence (PRBS), current-mode logic (CML), built-in self-test (BIST |
Field | DocType | ISSN |
Gigabit,Computer science,Pseudorandom binary sequence,Chip,Electronic engineering,CMOS,Multi channel,Modulation,Built-in self-test,Power consumption | Conference | 2163-9612 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chi-Hsien Wu | 1 | 0 | 0.34 |
| Jau-Ji Jou | 2 | 0 | 1.01 |
| Hsin-Wen Ting | 3 | 41 | 8.81 |
| Shao-I Chu | 4 | 0 | 0.68 |
| Bing Hong Liu | 5 | 36 | 4.91 |