Name
Abstract | ||
|---|---|---|
In this paper, we present an optimization method for threshold logic networks (TLNs) based on observability don't care (ODC)-based node merging. The method is adapted from an ATPG-based node-merging approach that works for conventional Boolean logic networks. To extend the approach for TLNs, we propose a method for computing the mandatory assignments of a stuck-at fault test on a threshold gate and a method for conducting logic implication in a TLN. The experimental results show that the proposed optimization method can save an average of approximately 2% threshold gates for a set of TLNs which are generated by using the latest TLN synthesis approach. The experimental results also demonstrate the efficiency of the proposed optimization method. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSI-DAT.2018.8373232 | 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | Field | DocType |
optimization method,threshold logic networks,ODC,threshold gate,logic implication,observability don't care-based node merging,ATPG-based node-merging approach,Boolean logic networks,stuck-at fault test,TLN synthesis approach | Boolean function,Data structure,Automatic test pattern generation,Logic gate,Observability,Computer science,Electronic engineering,Theoretical computer science,Boolean algebra,Merge (version control) | Conference |
ISSN | ISBN | Citations |
2474-2724 | 978-1-5386-4261-0 | 0 |
PageRank | References | Authors |
0.34 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fu-Lian Wong | 1 | 0 | 0.34 |
| Li-Cheng Zheng | 2 | 0 | 1.35 |
| Yung-Chih Chen | 3 | 413 | 39.89 |