Name
Abstract | ||
|---|---|---|
We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache. |
Year | Venue | Field |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | Control theory,Computer science,Cache,Voltage,Real-time computing,Electronic engineering,Headroom (audio signal processing),Fault prevention,Electronic circuit,Embedded system,Power consumption,Voltage droop |
DocType | ISSN | Citations |
Conference | 2162-7541 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pei-Yuan Chou | 1 | 6 | 1.87 |
| I-Chen Wu | 2 | 208 | 55.03 |
| Jai-Wei Lin | 3 | 0 | 0.34 |
| Xuan-Yu Lin | 4 | 0 | 0.68 |
| Tien-Fu Chen | 5 | 4 | 1.41 |
| Tay-Jyi Lin | 6 | 139 | 24.36 |
| Jinn-Shyan Wang | 7 | 536 | 103.75 |