Name
Abstract | ||
|---|---|---|
In this paper, a 1.25 Gpbs all-digital burst-mode clock and data recovery (BM-CDR) circuit with embedded time-to-digital converter (TDC) is presented. The proposed BM-CDR circuit uses an amendatory calculation method to achieve less quantization error. Current-starved inverters with control signals are used to realize fine-TDC to improve the resolution and reduce the power. This circuit is implemented in a 65nm CMOS process. Simulation results show that the clock jitter is reduced from 0.24 UI to 0.027 UI, about 88.75% under 16-bit consecutive identical digits. |
Year | Venue | Keywords |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | burst-mode clock and data recovery (BM-CDR), time-to-digital converter (TDC), current-starved inverter, low-power |
Field | DocType | ISSN |
Burst mode (photography),Computer science,Real-time computing,Cmos process,Electronic engineering,Data recovery,Jitter,Quantization (signal processing) | Conference | 2162-7541 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mengyin Jiang | 1 | 0 | 0.68 |
| Yuan Wang | 2 | 17 | 13.39 |
| Baoguang Liu | 3 | 4 | 1.92 |
| Yuequan Liu | 4 | 0 | 1.69 |
| Song Jia | 5 | 6 | 7.00 |
| zhang | 6 | 10 | 9.77 |