Name
Title | ||
|---|---|---|
Design On Multi-Bit Adder Using Sense Amplifier-Based Pass Transistor Logic For Near-Threshold Voltage Operation |
Abstract | ||
|---|---|---|
This paper proposes a new 16-bit adder which has a wide operating voltage range and higher energy efficiency for near-threshold voltage operation. This adder employs the architecture of carry look ahead (CLA) and gates of sense-amplifier based pass-transistor logic (SAPTL). Three other designs applying the same architecture and traditional logic gates (that is, double pass-transistor logic (DPL) gates and static CMOS logic gates) are also analyzed for comparison. The results of delay, power consumption and other related performances are analyzed especially in near-threshold voltage region. These adders have been successfully verified in a 65-nm CMOS process by post-layout simulations and all analysis are based on these simulation results. |
Year | Venue | Keywords |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | Near-threshold voltage (NTV), low-power, sense amplifier, double pass-transistor logic (DPL), multi-bit adder |
Field | DocType | ISSN |
Logic gate,Adder,Pass transistor logic,AND-OR-Invert,Computer science,Electronic engineering,CMOS,Serial binary adder,Logic level,Logic family,Electrical engineering | Conference | 2162-7541 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fangyuan Dang | 1 | 0 | 0.34 |
| Yuan Wang | 2 | 17 | 13.39 |
| Yuequan Liu | 3 | 0 | 1.69 |
| Song Jia | 4 | 6 | 7.00 |
| zhang | 5 | 10 | 9.77 |