Name
Abstract | ||
|---|---|---|
Newest technologies of integrated circuits manufacture allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a communication architecture with high scalability and a high degree of parallelism, such as a Network-on-Chip (NoC). As the integration technology scales down, the probability of Multiple Cell Upsets (MCUs) increases. NoC buffers are exposed to MCUs induced by different sources. In this paper, we evaluate Error Correction Codes (ECCs) to protect NoC buffers from permanent MCUs. We guide our evaluation to measure the area and power overhead of each implementation of ECC, as well as their correction and detection rates. We conducted experiments varying buffer parameters (16 and 32-bits flit length) and three different protection codes. The results show that the costs of adding an ECC in each input buffer of the NoC are justified by the decrease of error occurrence for systems exposed to MCU events. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/LASCAS.2017.7948071 | 2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS) |
Keywords | Field | DocType |
Network on chips,Fault Tolerance,Error Correction Code | Computer science,Degree of parallelism,Chip,Electronic engineering,Error detection and correction,Redundancy (engineering),Microcontroller,Transistor,Integrated circuit,Scalability,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-5090-5860-0 | 2 | 0.40 |
References | Authors | |
9 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Felipe Silva | 1 | 3 | 1.78 |
| Walter Magalhaes | 2 | 2 | 0.40 |
| Jarbas Silveira | 3 | 20 | 6.62 |
| Joao Marcelo Ferreira | 4 | 8 | 2.22 |
| Philippe de S. Magalhaes | 5 | 3 | 0.80 |
| Otávio A. de Lima | 6 | 2 | 0.40 |
| Cesar A. M. Marcon | 7 | 120 | 28.83 |