Name
Title | ||
|---|---|---|
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support |
Abstract | ||
|---|---|---|
Redundant binary to two's complement conversion circuits tailored for high speed FPGA implementations using a fabric aware approach for serial and carry look-ahead modes have been presented in this paper. The configured, yet underutilized FPGA logic slices are targeted for appendage of fault localization circuitry, namely, unidirectional or bidirectional scan path, C-testability and alternating logic without any logic overhead. The circuit descriptions have been automated and the design flow to determine the faulty FPGA slice coordinates have been proposed. The circuits have been realized through target FPGA specific primitive instantiation coupled with placement constraints to guarantee high speed design, as well as to ease out the exercise of locating faulty FPGA slice coordinates (if any). |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/IPDPSW.2018.00042 | 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Keywords | Field | DocType |
FPGA,Carry chain,Look-Up Table,Redundant number,Scan path,Fault Localization | Computer science,Parallel computing,Field-programmable gate array,Design flow,Fpga implementations,Computer hardware,Electronic circuit,Two's complement,Encoding (memory),Binary number | Conference |
ISSN | ISBN | Citations |
2164-7062 | 978-1-5386-5556-6 | 0 |
PageRank | References | Authors |
0.34 | 5 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ayan Palchaudhuri | 1 | 11 | 7.67 |
| Anindya Sundar Dhar | 2 | 97 | 26.09 |