Name
Abstract | ||
|---|---|---|
Traditional input-queued routers in network-on-chips (NoCs) only have a small number of virtual channels (VCs) and packets in a VC are organized in a fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the switch allocator. Since switch allocation is the critical pipeline stage in on-chip routers, HoL blocking significan... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TPDS.2018.2817552 | IEEE Transactions on Parallel and Distributed Systems |
Keywords | Field | DocType |
Resource management,Switches,Pipelines,Scheduling,Network-on-chip,Complexity theory | Latency (engineering),Computer science,Network packet,Network on a chip,Computer network,Latency (engineering),Router,Allocator,Re-order buffer,Performance improvement,Distributed computing | Journal |
Volume | Issue | ISSN |
29 | 9 | 1045-9219 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cunlu Li | 1 | 5 | 4.48 |
| Dezun Dong | 2 | 178 | 31.90 |
| Zhonghai Lu | 3 | 1063 | 100.12 |
| Xiangke Liao | 4 | 622 | 74.79 |