Name
Abstract | ||
|---|---|---|
In this brief, a half-rate (HR) bang-bang (BB) phase detector (PD) with multiple decision levels is proposed for clock and data recovery (CDR) circuits. The combination allows the oscillator to run at half the input data rate while providing information about the sign and magnitude of the phase shift between the PD inputs. This allows a liner control of the frequency of the oscillator in the phase... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TVLSI.2018.2826440 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Clocks,Logic gates,Partial discharges,Voltage-controlled oscillators,Topology,Detectors,Jitter | Phase-locked loop,Half Rate,Computer science,CMOS,Electronic engineering,Phase detector,Jitter,Electronic circuit,Detector,Bit error rate | Journal |
Volume | Issue | ISSN |
26 | 9 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Gimeno | 1 | 19 | 12.26 |
| David Bol | 2 | 162 | 27.67 |
| Denis Flandre | 3 | 316 | 70.47 |