Name
Abstract | ||
|---|---|---|
High-volume manufacturing of integrated circuits is what drives the semiconductor industry and the scaling of CMOS; however, shrinking all feature sizes is not optimal for all product volumes and applications. While scaling transistors provide improvement in performance at power in general, concerted scaling of the back-end-of-line (BEOL) interconnects provides improvement in density but at some e... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TVLSI.2018.2828387 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Wires,Capacitance,Couplings,Metals,Silicon,Integrated circuit interconnections,Routing | Capacitance,Computer science,Signal integrity,Chip,CMOS,Electronic engineering,Transistor,Scaling,Integrated circuit,Design for manufacturability | Journal |
Volume | Issue | ISSN |
26 | 9 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samuel N. Pagliarini | 1 | 14 | 4.96 |
| Mehmet Meric Isgenc | 2 | 3 | 2.41 |
| Mayler G. A. Martins | 3 | 88 | 10.08 |
| Lawrence T. Pileggi | 4 | 9 | 2.71 |