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SAMUEL N. PAGLIARINI
Author Info
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Name
Affiliation
Papers
SAMUEL N. PAGLIARINI
Univ Bristol, Dept Comp Sci, Bristol, Avon, England
13
Collaborators
Citations
PageRank
31
14
4.96
Referers
Referees
References
55
165
60
Search Limit
100
165
Publications (13 rows)
Collaborators (31 rows)
Referers (55 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Split-Chip Design to Prevent IP Reverse Engineering
0
0.34
2021
Side-Channel Attacks on Triple Modular Redundancy Schemes
0
0.34
2021
Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO
0
0.34
2021
Latch-Based Logic Locking
0
0.34
2020
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration.
0
0.34
2020
A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks.
1
0.36
2020
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes.
0
0.34
2020
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography.
0
0.34
2019
Application and Product-Volume-Specific Customization of BEOL Metal Pitch.
0
0.34
2018
A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.
12
0.83
2017
Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits
1
0.39
2017
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ
0
0.34
2017
Design And Analysis Of Binary Tree Static Random Access Memory For Low Power Embedded Systems
0
0.34
2014
1