Name
Abstract | ||
|---|---|---|
With the increasing complexity of modern systems-on-chip, the possibility of functional errors escaping design verification is growing. Postsilicon validation targets the discovery of these errors in early hardware prototypes. Due to limited visibility and observability, dedicated design-for-debug (DFD) hardware, such as trace buffers, is inserted to aid postsilicon validation. In spite of its ben... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TVLSI.2018.2827928 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Hardware,Buffer storage,Instruction sets,Computer bugs,Standards,Pipelines,Proposals | Control theory,Observability,Reuse,Computer science,Instruction set,Software bug,Real-time computing,Thread (computing),Simultaneous multithreading,Overhead (business),Embedded system | Journal |
Volume | Issue | ISSN |
26 | 9 | 1063-8210 |
Citations | PageRank | References |
1 | 0.36 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Neetu Jindal | 1 | 6 | 1.48 |
| Preeti Ranjan Panda | 2 | 786 | 89.40 |
| Smruti R. Sarangi | 3 | 447 | 41.94 |