Name
Title | ||
|---|---|---|
220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2<sup>4</sup>)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS |
Abstract | ||
|---|---|---|
A reconfigurable AES/SMS4/Camellia symmetric-key cipher accelerator fabricated in 14nm CMOS achieves 3.17/2.68/3.17 Gbps throughput at 750mV, 25°C. Hybrid GF(2
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup>
)
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
Sbox-based unified datapath with in-line key expansion, polynomial optimization, scaled affine transform assisted multiply-less MixColumns with key-precompute, and shared round constant circuits result in a 9152 μm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
design, a 29% area reduction over conventional separate implementations. Look-up-table (LUT) elimination enables sub-threshold operation down to 220mV, with 794/584/754Gbps/W peak energy-efficiency measured at 240mV. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/VLSIC.2018.8502262 | 2018 IEEE Symposium on VLSI Circuits |
Keywords | DocType | ISSN |
14NM tri-gate CMOS,in-line key expansion,key-precompute,794-584-754Gbps-W peak energy-efficiency,Sbox-based unified datapath,hybrid GF,reconfigurable AES-SMS4-Camellia symmetric-key cipher accelerator,AES-SMS4-Camellia symmetric-key cipher accelerator,220MV-900MV 794-584-754 GBPS-W reconfigurable GF | Conference | 2158-5601 |
ISBN | Citations | PageRank |
978-1-5386-4215-3 | 0 | 0.34 |
References | Authors | |
0 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sudhir Satpathy | 1 | 269 | 19.69 |
| Vikram B. Suresh | 2 | 31 | 10.23 |
| S. Mathew | 3 | 462 | 76.59 |
| Mark Anders | 4 | 315 | 50.81 |
| Himanshu Kaul | 5 | 456 | 51.07 |
| Amit Agarwal | 6 | 693 | 72.95 |
| S. K. Hsu | 7 | 521 | 52.06 |
| Ram Krishnamurthy | 8 | 650 | 74.63 |