Paper Info
Title
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and V<inf>OH</inf>Calibration in 20NM DRAM Process
Abstract
A sub-0.85V, 6.4Gb/s TX-interleaved transceiver with fast wake-up time using 2-step charging control and a V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OH</inf> calibration scheme is implemented using 20nm DRAM process. Adopting an interleaving scheme based on improved DRAM process, the proposed design operates at lowest supply voltage of 0.83V in DRAM process, and improves pin-efficiency by 30% compared with recent DRAM I/O interfaces. The fast wake-up time level shifter can achieve target switching voltage level without latency increase. And the leakage current by newly adopted transistors can be alleviated using a splitted power gating scheme.
Year
DOI
Venue
2018
10.1109/VLSIC.2018.8502299
2018 IEEE Symposium on VLSI Circuits
Keywords
DocType
ISSN
2-step charging control,interleaving scheme,TX-interleaved transceiver,DRAM process,fast wake-up time level,voltage 0.85 V,size 20.0 nm,voltage 0.83 V
Conference
2158-5601
ISBN
Citations 
PageRank 
978-1-5386-4215-3
0
0.34
References 
Authors
0
26
Name
Order
Citations
PageRank
Jin-Hyeok Baek101.01
Chang-Kyo Lee233.52
Kiho Kim335536.32
daesik moon4163.87
Gil-Hoon Cha500.68
Jinseok Heo663.05
Min-Su Ahn721.91
Dong-Ju Kim800.34
Jae-Joon Song900.34
Seokhong Kwon1010.75
Jongmin Kim1110.75
Kyung-Soo Kim1200.34
Jinoh Ahn1300.34
Jeong-Sik Nam1400.34
Byungcheol Kim1500.68
Jeong-Hyeon Cho1631.77
Jeonghoon Oh1700.34
Seung-Jun Bae1816732.40
Indal Song1900.34
Seok-Hun Hyun2022.79
Ilgweon Kim2100.34
Hyuck-Joon Kwon2222.44
Young-Soo Sohn2351.33
Jung-Hwan Choi2400.34
Kwang-Il Park2500.34
Seong-Jin Jang2600.68