Name
Title | ||
|---|---|---|
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification |
Abstract | ||
|---|---|---|
Non-scan based test generation is required to reduce test cost and improve security. However, sequential test generation consumes a lot of time to identify untestable faults. Therefore, it is important to identify untestable faults in the preprocessing of the test generation. In this paper, an unreachable state identification method, which identifies whether states on a few flip-flops can be justified using SAT, and an untestable fault identification method using the unreachable states are proposed. Experimental results show that our proposed method was effective compared with conventional methods. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/IOLTS.2018.8474268 | 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) |
Keywords | Field | DocType |
unreachable states,untestable faults,state cube justification,SAT | Sequential logic,Computer science,Test pattern generators,Real-time computing,Preprocessor,Computer engineering,Cube | Conference |
ISBN | Citations | PageRank |
978-1-5386-5993-9 | 0 | 0.34 |
References | Authors | |
7 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toshinori Hosokawa | 1 | 84 | 16.12 |
| Morito Niseki | 2 | 0 | 0.34 |
| Masayoshi Yoshimura | 3 | 29 | 6.98 |
| Hiroshi Yamazaki | 4 | 7 | 3.28 |
| M. Arai | 5 | 6 | 7.63 |
| Hiroyuki Yotsuyanagi | 6 | 70 | 19.04 |
| Masaki Hashizume | 7 | 98 | 27.83 |