Name
Abstract | ||
|---|---|---|
This paper presents a 112 Gb/s PAM4 CMOS linear TIA to meet the requirements of emerging 400G Ethernet standards for data center interconnect. A regulated inverter-based amplifier with inductive shunt feedback is used to realize a high bandwidth, low noise front-end in 28 nm bulk CMOS process. A VGA accommodates input currents up to 1 mA(pp) with <5% THD, and a 72 GHz post-amplifier chain delivers 300 mV(pp) output swing. The TIA provides 65 dB Omega trans-impedance gain with 4.7 mu A(rms) input referred noise while dissipating 107 mW. Careful optimization of distributed inductive peaking ensures <5 ps group delay variation over 45 GHz. Standalone electrical measurements verify the ability of the TIA to receive 112 Gb/s PAM4 data with an energy efficiency of 0.96 pJ/bit, showing the potential for single-chip CMOS transceiver solutions for next-generation data center applications. |
Year | Venue | Keywords |
|---|---|---|
2018 | Proceedings of the European Solid-State Circuits Conference | TIA,optical receiver,400G Ethernet,PAM4,shunt feedback TIA |
Field | DocType | ISSN |
Inverter,Transceiver,Computer science,Group delay and phase delay,Electronic engineering,CMOS,Video Graphics Array,Integrated circuit,Silicon-germanium,Amplifier | Conference | 1930-8833 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao Li | 1 | 35 | 6.55 |
| Ganesh Balamurugan | 2 | 144 | 20.77 |
| James E. Jaussi | 3 | 125 | 26.64 |
| Bryan Casper | 4 | 147 | 25.64 |