Name
Title | ||
|---|---|---|
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. |
Abstract | ||
|---|---|---|
3D TSV integration enables scalable manycore architectures, however they require advanced cache coherence features to enable simple programming models. We propose TSARLET, a general purpose 16-core computing fabric targeting 3D TSV integration with a fully scalable cache coherent memory architecture, using distributed L2-caches, and adaptive fault tolerant L3-caches. Implemented in 28nm UTBB FDSOI technology, the circuit operates up to 1.15 GHz using adaptive clocking and provides 29 Gops/W in the 0.5-1.3V supply range. The chip's performance is demonstrated using an image filter application and an OpenMP based Convolutional Neural Network (CNN) on Linux. |
Year | Venue | Keywords |
|---|---|---|
2018 | Proceedings of the European Solid-State Circuits Conference | 3D integration,cache coherence,FDS01,CNN |
Field | DocType | ISSN |
Fabric computing,Computer architecture,Programming paradigm,Computer science,Cache,Electronic engineering,Chip,Fault tolerance,Memory architecture,Cache coherence,Scalability | Conference | 1930-8833 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
12 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eric Guthmuller | 1 | 19 | 3.80 |
| César Fuguet Tortolero | 2 | 5 | 2.89 |
| Pascal Vivet | 3 | 606 | 53.09 |
| Christian Bernard | 4 | 46 | 5.36 |
| Ivan Miro Panades | 5 | 96 | 7.81 |
| Jean Durupt | 6 | 55 | 6.43 |
| E. Beignc | 7 | 0 | 0.34 |
| Didier Lattard | 8 | 144 | 18.68 |
| Séverine Cheramy | 9 | 22 | 4.74 |
| Alain Greiner | 10 | 3 | 1.13 |
| Quentin Meunier | 11 | 10 | 5.31 |
| Pirouz Bazargan-Sabet | 12 | 4 | 2.47 |