Name
Abstract | ||
|---|---|---|
This article presents an automated approach for detecting system- level bugs in SoC designs that are composed of many IP blocks, without exposing sensitive information. The approach leverages high-level synthesis techniques. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/MDAT.2018.2824121 | IEEE Design & Test |
Keywords | Field | DocType |
Computer bugs,Hardware,IP networks,Intellectual property,Hardware design languages | Software engineering,Computer science,High-level synthesis,Software bug,Virginia tech,Software,Information sensitivity,Computer engineering,Hardware design languages | Journal |
Volume | Issue | ISSN |
35 | 5 | 2168-2356 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pietro Fezzardi | 1 | 1 | 0.70 |
| Fabrizio Ferrandi | 2 | 548 | 56.95 |
| Christian Pilato | 3 | 329 | 32.19 |