Name
Abstract | ||
|---|---|---|
In this work, trade-offs between performance and reliability in CMOS RF power amplifiers at the design stage are studied. The impact of transistor sizing, amplifier class and on-chip matching network design are explored for a 130 nm technology and the implications of design decisions in transistor gate oxide reliability are discussed and projected. A strong trade-off is observed between efficiency and reliability, mainly for different on-chip output matching architectures. A comparison between two example designs is performed via SPICE simulations that include reliability models and the effects of aging on the stress conditions of each amplifier. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1016/j.microrel.2018.06.089 | Microelectronics Reliability |
Keywords | Field | DocType |
Power amplifier,Breakdown,Hot carriers,Design | Network planning and design,Spice,Electronic engineering,CMOS,Trade offs,Gate oxide,Engineering,Transistor,RF power amplifier,Amplifier | Journal |
Volume | ISSN | Citations |
88 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sebastián Matías Pazos | 1 | 0 | 0.34 |
| F. L. Aguirre | 2 | 0 | 0.34 |
| F. Palumbo | 3 | 5 | 3.72 |
| Fernando Silveira | 4 | 36 | 16.18 |