Paper Info
Title
Impact of sidewall etching on the dynamic performance of GaN-on-Si E-mode transistors.
Abstract
The aim of this paper is to investigate the role of the etching of the sidewalls of p-GaN on the dynamic performance of normally-off GaN HEMTs with p-type gate. We analyze two wafers having identical epitaxy but with different recipes for the sidewall etching, referred to as “Etch A” (non-optimized) and “Etch B” (optimized). We demonstrate the following relevant results: (i) the devices with non-optimized etching (Etch A), when submitted to positive gate bias, show a negative threshold voltage shift and a decrease in Ron, which are ascribed to hole injection under the gate and/or in the access regions; (ii) transient characterization indicates the existence of two trap states, with activation energies of 0.84 eV (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</inf> defects) and 0.30 eV. The latter (with time-constants in the ms range) is indicative of the hole de-trapping process, possibly related to trap states in the AlGaN barrier or at the passivation/AlGaN interface; (iii) by optimizing the p-GaN sidewall etching (for the same epitaxy) it is possible to completely eliminate the threshold voltage shift. This indicates that hole injection mostly takes place on the sidewalls.
Year
DOI
Venue
2018
10.1016/j.microrel.2018.06.037
Microelectronics Reliability
Keywords
Field
DocType
GaN,High-electron-mobility transistor,p-GaN gate,Threshold voltage shift,Trapping mechanism
Wafer,Etching,Electronic engineering,Engineering,Transistor,Passivation,Optoelectronics,Threshold voltage,Epitaxy
Journal
Volume
ISSN
ISBN
88
0026-2714
978-1-5386-9504-3
Citations 
PageRank 
References 
0
0.34
1
Authors
8
Name
Order
Citations
PageRank
Alaleh Tajalli111.30
E. Canato211.64
A. Nardo300.34
Matteo Meneghini44530.20
Arno Stockman500.34
P. Moens6118.32
Enrico Zanoni76037.05
Gaudenzio Meneghesso86738.27