Name
Abstract | ||
|---|---|---|
Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage. The proposed framework integrates the widely used LLVM compiler infrastructure and the increasingly popular RISC-V FPGA soft-processor. The compiler automatically generates custom instructions in the security critical segments of the program, and the instructions execute on the RISC-V custom co-processor to produce diversified timing characteristics on each execution instance. CIDPro has been implemented on the Zynq7000 XC7Z020 FPGA device to study the performance overhead and security tradeoffs. Experimental results show that our solution can achieve 80% and 86% timing side-channel capacity reduction for two benchmarks with an acceptable performance overhead compared to existing solutions. In addition, the proposed method incurs only a negligible hardware area overhead of 1% slices of the entire RISC-V system. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/FPL.2018.00045 | 2018 28th International Conference on Field Programmable Logic and Applications (FPL) |
Keywords | DocType | Volume |
Hardware diversification,Custom Instructions,RISC V,Timing side channels,Software obfuscation | Conference | abs/1809.01221 |
ISSN | ISBN | Citations |
1946-147X | 978-1-5386-8518-1 | 0 |
PageRank | References | Authors |
0.34 | 10 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thinh H. Pham | 1 | 22 | 4.57 |
| Alexander Fell | 2 | 66 | 8.66 |
| arnab kumar biswas | 3 | 29 | 4.57 |
| Siew-Kei Lam | 4 | 99 | 14.60 |
| Nandeesha Veeranna | 5 | 0 | 0.34 |