Name
Abstract | ||
|---|---|---|
Reduction of power loss in circuit operation is an urgent task to save energy. For this purpose accurate prediction of the device-level power loss is a prerequisite. The core compact modeling approach is presented, which can be easily extended to include non-ideal effects to be considered. With use of the developed model it is demonstrated that any phenomena, which prevent the gate control, become the origin of an increased power loss. An optimization scheme for achieving low power loss, based on the presented compact modeling approach, is discussed with basic circuits. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ESSDERC.2018.8486858 | 2018 48th European Solid-State Device Research Conference (ESSDERC) |
Keywords | Field | DocType |
MOSFETs,compact modeling,power loss,carrier dynamics,circuit performance | Logic gate,Power efficient,Semiconductor device modeling,Circuit design,Gate control,Electronic engineering,Power loss,Electronic circuit,MOSFET,Materials science | Conference |
ISSN | ISBN | Citations |
1930-8876 | 978-1-5386-5402-6 | 0 |
PageRank | References | Authors |
0.34 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mitiko Miura-Mattausch | 1 | 11 | 16.18 |
| Hideyuki Kikuchihara | 2 | 7 | 2.85 |
| T. Kajiwara | 3 | 0 | 0.34 |
| Yuta Tanimoto | 4 | 0 | 1.01 |
| Atsushi Saito | 5 | 0 | 0.68 |
| Takahiro Iizuka | 6 | 2 | 3.79 |
| Dondee Navarro | 7 | 3 | 3.90 |
| Hans Jürgen Mattausch | 8 | 96 | 32.93 |