Title | ||
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Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus. |
Abstract | ||
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Hardware architectures for Spiking Neural Networks (SNNs) emulation exhibit accelerated processing thanks to their massive parallelism. However, configuring multichip platforms and setting up a neural application can be an abstract and rigid procedure. In this paper, a simple and efficient centralized configuration solution for a scalable multichip platform based on FPGA and PSoC devices is presented. For this purpose, a dedicated Master Device (MD) node has been used to configure a scalable network of Neuromorphic Devices (NDs). The NDs are general purpose devices which can be programmed to execute any neural algorithm based on spikes with a customized synapse topology. In the proposed approach, the communication channel is re-utilized and the Address Representation Event (AER) protocol modified to configure the entire system. This approximation allows achieving area and power consumption optimization since it eliminates the need to implement a specific instance per chip. Simulations shown demonstrate the performance and temporal characterization of this proposal. |
Year | Venue | Keywords |
---|---|---|
2018 | NASA/ESA Conference on Adaptive Hardware and Systems | Configurability,FPGA,PSoC,SNN emulation,AER (Address Event Representation),multi-chip platform |
Field | DocType | ISSN |
Massively parallel,Computer science,Neuromorphic engineering,Field-programmable gate array,Chip,Real-time computing,Emulation,Spiking neural network,PSoC,Embedded system,Scalability | Conference | 1939-7003 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 |
Name | Order | Citations | PageRank |
---|---|---|---|
mireya zapata | 1 | 9 | 3.45 |
Janio Jadan | 2 | 0 | 0.34 |
Jordi Madrenas | 3 | 150 | 27.87 |