Paper Info
Title
A survey of techniques for improving error-resilience of DRAM.
Abstract
Aggressive process scaling and increasing demands of performance/cost efficiency have exacerbated the incidences and impact of errors in DRAM systems. Due to this, improvements in DRAM reliability has received significant attention in recent years from both academia and industry. In this paper, we present a survey of techniques for improving reliability of DRAM-based main memory. We classify the works based on key parameters to emphasize their similarities and differences. This paper is expected to be useful for computer architects, chip-designers and researchers in the area of memory/system-reliability.
Year
DOI
Venue
2018
10.1016/j.sysarc.2018.09.004
Journal of Systems Architecture
Keywords
Field
DocType
DRAM,Reliability,Memory,Error correcting code (ECC),Chipkill,Stacked DRAM,In-DRAM ECC,Data compression
Psychological resilience,Dram,Computer science,Real-time computing,Reliability engineering,Cost efficiency
Journal
Volume
ISSN
Citations 
91
1383-7621
2
PageRank 
References 
Authors
0.35
53
2
Name
Order
Citations
PageRank
Sparsh Mittal181750.36
Maruthi S. Inukonda220.35