Title | ||
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A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. |
Abstract | ||
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The RISC-V Instruction Set Architecture (ISA) is becoming an increasingly popular ecosystem for both hardware and software development. In this article, we investigate one of RISC-V’s most versatile ISA extensions, which allows for compressed 16-bit instructions to coexist with regular 32-bit instructions. While the use of instruction compression has been touted as a means to primarily reduce code density, we present another beneficial exploitation avenue: dual issuing of compressed 16-bit instructions with minimal hardware overhead. Consequently, the proposed RISC-V processor design can substantially improve instruction throughput and reduce execution times. Additionally, the new processor employs selective register renaming to specifically target the registers used under instruction compression, thereby completely eliminating unnecessary stalls due to name dependencies. Finally, the new design utilizes a partitioned register file that capitalizes on the skewed use of registers to improve energy efficiency through clock gating. Extensive hardware analysis and cycle-accurate simulations using real applications demonstrate the effectiveness of the proposed processor architecture. Dual issuing of compressed instructions is shown to often approach the performance of a full-width two-way superscalar processor, but with much higher area and power efficiency; this is of paramount importance to severely resource-restricted emerging paradigms, such as wearable devices and Internet-of-Things (IoT) environments. |
Year | DOI | Venue |
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2018 | 10.1016/j.micpro.2018.05.007 | Microprocessors and Microsystems |
Keywords | Field | DocType |
RISC-V,Microprocessor design,Processor architecture,Register renaming,Instruction compression | RISC-V,Clock gating,Computer science,Instruction set,Parallel computing,Register file,Processor design,Register renaming,Multi-core processor,Embedded system,Microarchitecture | Journal |
Volume | ISSN | Citations |
61 | 0141-9331 | 5 |
PageRank | References | Authors |
1.32 | 2 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Karyofyllis Patsidis | 1 | 5 | 1.65 |
Dimitris Konstantinou | 2 | 6 | 2.36 |
Chrysostomos Nicopoulos | 3 | 835 | 50.37 |
Giorgos Dimitrakopoulos | 4 | 215 | 27.31 |